All Outputs (4)

Pipelined streaming computation of histogram in FPGA OpenCL (2018)
Conference Proceeding
Hosseinabady, M., & Nunez-Yanez, J. L. (2018). Pipelined streaming computation of histogram in FPGA OpenCL. In S. Bassini, M. Danelutto, P. Dazzi, G. R. Joubert, & F. Peters (Eds.), Parallel Computing is Everywhere (632-641). https://doi.org/10.3233/978-1-61499-843-3-632

The emergence of High-Level Synthesis (HLS) techniques and tools, along with new features in high-end FPGAs such as multi-port memory interfaces, has enabled designers to utilize FPGAs not only for compute-bound but also for memory-bound tasks. This... Read More about Pipelined streaming computation of histogram in FPGA OpenCL.

Dynamic energy management of FPGA accelerators in embedded systems (2018)
Journal Article
Hosseinabady, M., & Nunez-Yanez, J. L. (2018). Dynamic energy management of FPGA accelerators in embedded systems. ACM Transactions on Embedded Computing Systems, 17(3), Article 63. https://doi.org/10.1145/3182172

In this article, we investigate how to utilise an Field-Programmable Gate Array (FPGA) in an embedded system to save energy. For this purpose, we study the energy efficiency of a hybrid FPGA-CPU device that can switch task execution between hardware... Read More about Dynamic energy management of FPGA accelerators in embedded systems.

Multi-precision convolutional neural networks on heterogeneous hardware (2018)
Conference Proceeding
Amiri, S., Hosseinabady, M., McIntosh-Smith, S., & Nunez-Yanez, J. (2018). Multi-precision convolutional neural networks on heterogeneous hardware. In 2018 Design, Automation & Test in Europe Conference & Exhibition (419-424). https://doi.org/10.23919/DATE.2018.8342046

Fully binarised convolutional neural networks (CNNs) deliver very high inference performance using single-bit weights and activations, together with XNOR type operators for the kernel convolutions. Current research shows that full binarisation result... Read More about Multi-precision convolutional neural networks on heterogeneous hardware.

Simultaneous multiprocessing in a software-defined heterogeneous FPGA (2018)
Journal Article
Nunez-Yanez, J., Amiri, S., Hosseinabady, M., Rodríguez, A., Asenjo, R., Navarro, A., …Gran, R. (2019). Simultaneous multiprocessing in a software-defined heterogeneous FPGA. Journal of Supercomputing, 75(8), 4078-4095. https://doi.org/10.1007/s11227-018-2367-9

Heterogeneous chips that combine CPUs and FPGAs can distribute processing so that the algorithm tasks are mapped onto the most suitable processing element. New software-defined high-level design environments for these chips use general purpose langua... Read More about Simultaneous multiprocessing in a software-defined heterogeneous FPGA.