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Simultaneous multiprocessing in a software-defined heterogeneous FPGA

Nunez-Yanez, Jose; Amiri, Sam; Hosseinabady, Mohammad; Rodríguez, Andrés; Asenjo, Rafael; Navarro, Angeles; Suarez, Dario; Gran, Ruben

Simultaneous multiprocessing in a software-defined heterogeneous FPGA Thumbnail


Authors

Jose Nunez-Yanez

Sam Amiri

Mohammad Hosseinabady

Andrés Rodríguez

Rafael Asenjo

Angeles Navarro

Dario Suarez

Ruben Gran



Abstract

Heterogeneous chips that combine CPUs and FPGAs can distribute processing so that the algorithm tasks are mapped onto the most suitable processing element. New software-defined high-level design environments for these chips use general purpose languages such as C++ and OpenCL for hardware and interface generation without the need for register transfer language expertise. These advances in hardware compilers have resulted in significant increases in FPGA design productivity. In this paper, we investigate how to enhance an existing software-defined framework to reduce overheads and enable the utilization of all the available CPU cores in parallel with the FPGA hardware accelerators. Instead of selecting the best processing element for a task and simply offloading onto it, we introduce two schedulers, Dynamic and LogFit, which distribute the tasks among all the resources in an optimal manner. A new platform is created based on interrupts that removes spin-locks and allows the processing cores to sleep when not performing useful work. For a compute-intensive application, we obtained up to 45.56% more throughput and 17.89% less energy consumption when all devices of a Zynq-7000 SoC collaborate in the computation compared against FPGA-only execution.

Citation

Nunez-Yanez, J., Amiri, S., Hosseinabady, M., Rodríguez, A., Asenjo, R., Navarro, A., …Gran, R. (2019). Simultaneous multiprocessing in a software-defined heterogeneous FPGA. Journal of Supercomputing, 75(8), 4078-4095. https://doi.org/10.1007/s11227-018-2367-9

Journal Article Type Article
Online Publication Date Apr 16, 2018
Publication Date Aug 1, 2019
Deposit Date Dec 11, 2023
Publicly Available Date Dec 12, 2023
Journal Journal of Supercomputing
Print ISSN 0920-8542
Electronic ISSN 1573-0484
Publisher Springer Verlag
Peer Reviewed Peer Reviewed
Volume 75
Issue 8
Pages 4078-4095
DOI https://doi.org/10.1007/s11227-018-2367-9
Public URL https://uwe-repository.worktribe.com/output/11511798

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