Roshan Weerasekera's Outputs (11)

Electrical signal transfer characteristics of mycelium-bound composites and fungal fruiting bodies (2024)
Journal Article

Mycelium-bound composites are normally made of discrete lignocellulosic substrate elements bound together by filamentous fungal hyphae. They can be formed into bespoke components of desired geometries by moulding or extrusion. Mycelium-bound composit... Read More about Electrical signal transfer characteristics of mycelium-bound composites and fungal fruiting bodies.

Propagation of electrical signals by fungi (2023)
Journal Article

Living fungal mycelium networks are proven to have properties of memristors, capacitors and various sensors. To further progress our designs in fungal electronics we need to evaluate how electrical signals can be propagated through mycelium networks.... Read More about Propagation of electrical signals by fungi.

Sport-related back injury prevention with a wearable device (2022)
Journal Article

There has been a high incidence rates (∼41%) of back injury from undertaking weightlifting exercises as a result of improper lifting posture, where the spine should remain straight during a lifting movement which is often not adopted correctly by ado... Read More about Sport-related back injury prevention with a wearable device.

Contactless sensing of liquid marbles for detection, characterisation & computing (2019)
Journal Article

Liquid marbles (LMs) are of growing interest in many fields, including microfluidics, microreactors, sensors, and signal carriers. The generation of LMs is generally performed manually, although there has recently been a burst of publications involvi... Read More about Contactless sensing of liquid marbles for detection, characterisation & computing.

Neuromorphic liquid marbles with aqueous carbon nanotube cores (2019)
Journal Article

Neuromorphic computing devices attempt to emulate features of biological nervous systems through mimicking the properties of synapses, towards implementing the emergent properties of their counterparts, such as learning. Inspired by recent advances i... Read More about Neuromorphic liquid marbles with aqueous carbon nanotube cores.

Semiconductor package and method of forming the same (2019)
Patent

An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate (2016)
Journal Article

© 2016 IEEE. Through-silicon via (TSV) is an integral part of 2.5-D IC technology leveraged for multichip heterogeneous integration to achieve shorter interconnects, faster speed, and lower power consumption in the state-of-the-art circuit systems. T... Read More about An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate.

Heterogeneous 2.5D integration on through silicon interposer (2015)
Journal Article

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry... Read More about Heterogeneous 2.5D integration on through silicon interposer.

Fabrication and assembly of Cu-RDL-based 2.5-D Low-Cost Through Silicon Interposer (LC-TSI) (2015)
Journal Article

A through silicon interposer (TSI) fabrication process and detailed characterization and measurement results of redistribution layers and through silicon vias for low-cost 2.5-D integration is reviewed. Polymer-based Cu-RDL interconnects provide a CM... Read More about Fabrication and assembly of Cu-RDL-based 2.5-D Low-Cost Through Silicon Interposer (LC-TSI).

A 9.8 Gbps, 6.5 mW forwarded-clock receiver with phase interpolator and equalized current sampler in 65 nm CMOS (2015)
Presentation / Conference Contribution

© 2015 IEEE. A full-rate energy-efficient forwarded-clock (FC) receiver is demonstrated in this paper. A current sampler with continuous-time equalization is realized with 20 GHz bandwidth in sampling for data recovery. Moreover, a phase interpolator... Read More about A 9.8 Gbps, 6.5 mW forwarded-clock receiver with phase interpolator and equalized current sampler in 65 nm CMOS.

BIST methodology, architecture and circuits for pre-bond TSV testing in 3D stacking IC systems (2014)
Journal Article

© 2004-2012 IEEE. This paper presents a built-in self test (BIST) methodology, architecture and circuits for testing Through Silicon Vias (TSVs) in 3D-IC systems prior to stacking in order to improve 3D-IC yield and reduce overall test cost. A scan s... Read More about BIST methodology, architecture and circuits for pre-bond TSV testing in 3D stacking IC systems.