All Outputs (8)

Run-time power modelling in embedded GPUs with dynamic voltage and frequency scaling (2020)
Presentation / Conference Contribution

This paper investigates the application of a robust CPU-based power modelling methodology that performs an automatic search of explanatory events derived from performance counters to embedded GPUs. A 64-bit Tegra TX1 SoC is configured with DVFS enabl... Read More about Run-time power modelling in embedded GPUs with dynamic voltage and frequency scaling.

Sparse matrix-dense matrix multiplication on heterogeneous CPU+FPGA embedded system (2020)
Presentation / Conference Contribution

Embedded intelligence is becoming the primary driver for new applications in industry, healthcare, and automotive, to name a few. The main characteristics of these applications are high computational demand, real-time interaction with the environment... Read More about Sparse matrix-dense matrix multiplication on heterogeneous CPU+FPGA embedded system.

A streaming dataflow engine for sparse matrix-vector multiplication using high-level synthesis (2019)
Journal Article

Using high-level synthesis techniques, this paper proposes an adaptable high-performance streaming dataflow engine for sparse matrix dense vector multiplication (SpMV) suitable for embedded FPGAs. As the SpMV is a memory-bound algorithm, this engine... Read More about A streaming dataflow engine for sparse matrix-vector multiplication using high-level synthesis.

Pipelined streaming computation of histogram in FPGA OpenCL (2018)
Presentation / Conference Contribution

The emergence of High-Level Synthesis (HLS) techniques and tools, along with new features in high-end FPGAs such as multi-port memory interfaces, has enabled designers to utilize FPGAs not only for compute-bound but also for memory-bound tasks. This... Read More about Pipelined streaming computation of histogram in FPGA OpenCL.

Dynamic energy management of FPGA accelerators in embedded systems (2018)
Journal Article

In this article, we investigate how to utilise an Field-Programmable Gate Array (FPGA) in an embedded system to save energy. For this purpose, we study the energy efficiency of a hybrid FPGA-CPU device that can switch task execution between hardware... Read More about Dynamic energy management of FPGA accelerators in embedded systems.

Multi-precision convolutional neural networks on heterogeneous hardware (2018)
Presentation / Conference Contribution

Fully binarised convolutional neural networks (CNNs) deliver very high inference performance using single-bit weights and activations, together with XNOR type operators for the kernel convolutions. Current research shows that full binarisation result... Read More about Multi-precision convolutional neural networks on heterogeneous hardware.

Simultaneous multiprocessing in a software-defined heterogeneous FPGA (2018)
Journal Article

Heterogeneous chips that combine CPUs and FPGAs can distribute processing so that the algorithm tasks are mapped onto the most suitable processing element. New software-defined high-level design environments for these chips use general purpose langua... Read More about Simultaneous multiprocessing in a software-defined heterogeneous FPGA.

Energy optimization in commercial FPGAs with voltage, frequency and logic scaling (2015)
Journal Article

This paper investigates the energy reductions possible in commercially available FPGAs configured to support voltage, frequency and logic scalability combined with power gating. Voltage and frequency scaling is based on in-situ detectors that allow t... Read More about Energy optimization in commercial FPGAs with voltage, frequency and logic scaling.