Skip to main content

Research Repository

See what's under the surface


Contactless sensing of liquid marbles for detection, characterisation & computing (2019)
Journal Article
Draper, T. C., Phillips, N., Weerasekera, R., Mayne, R., Fullarton, C., de Lacy Costello, B., & Adamatzky, A. (2020). Contactless sensing of liquid marbles for detection, characterisation & computing. Lab on a Chip, 20(1), 136-146. https://doi.org/10.1039/c9lc01001g

Liquid marbles (LMs) are of growing interest in many fields, including microfluidics, microreactors, sensors, and signal carriers. The generation of LMs is generally performed manually, although there has recently been a burst of publications involvi... Read More about Contactless sensing of liquid marbles for detection, characterisation & computing.

An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate (2016)
Journal Article
Weerasekera, R., Katti, G., Dutta, R., Zhang, S., Chang, K. F., Zhou, J., & Bhattacharya, S. (2016). An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate. IEEE Transactions on Electron Devices, 63(3), 1182-1188. https://doi.org/10.1109/TED.2016.2522501

© 2016 IEEE. Through-silicon via (TSV) is an integral part of 2.5-D IC technology leveraged for multichip heterogeneous integration to achieve shorter interconnects, faster speed, and lower power consumption in the state-of-the-art circuit systems. T... Read More about An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate.

Heterogeneous 2.5D integration on through silicon interposer (2015)
Journal Article
Zhang, X., Lin, J. K., Wickramanayaka, S., Zhang, S., Weerasekera, R., Dutta, R., …Kwong, D. L. (2015). Heterogeneous 2.5D integration on through silicon interposer. Applied Physics Reviews, 2(2), 021308. https://doi.org/10.1063/1.4921463

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry... Read More about Heterogeneous 2.5D integration on through silicon interposer.

A 9.8 Gbps, 6.5 mW forwarded-clock receiver with phase interpolator and equalized current sampler in 65 nm CMOS (2015)
Journal Article
Ma, S., Manoj, S., Yu, H., Ren, J., & Weerasekera, R. (2015). A 9.8 Gbps, 6.5 mW forwarded-clock receiver with phase interpolator and equalized current sampler in 65 nm CMOS. IEEE Mtt S International Microwave Symposium Digest, 1-4. https://doi.org/10.1109/MWSYM.2015.7166838

full-rate energy-efficient forwarded-clock (FC) receiver is demonstrated in this paper. A current sampler with continuous-time equalization is realized with 20 GHz bandwidth in sampling for data recovery. Moreover, a phase interpolator is introduced... Read More about A 9.8 Gbps, 6.5 mW forwarded-clock receiver with phase interpolator and equalized current sampler in 65 nm CMOS.

Fabrication and assembly of Cu-RDL-based 2.5-D Low-Cost Through Silicon Interposer (LC-TSI) (2015)
Journal Article
Lin, J. K., Chang, K. F., Zhang, S., Yu, L. H., Katti, G., Ho, S. W., …Bhattacharya, S. (2015). Fabrication and assembly of Cu-RDL-based 2.5-D Low-Cost Through Silicon Interposer (LC-TSI). IEEE Design and Test, 32(4), 23-31. https://doi.org/10.1109/MDAT.2015.2424429

A through silicon interposer (TSI) fabrication process and detailed characterization and measurement results of redistribution layers and through silicon vias for low-cost 2.5-D integration is reviewed. Polymer-based Cu-RDL interconnects provide a CM... Read More about Fabrication and assembly of Cu-RDL-based 2.5-D Low-Cost Through Silicon Interposer (LC-TSI).

BIST methodology, architecture and circuits for pre-bond TSV testing in 3D stacking IC systems (2014)
Journal Article
Wang, C., Zhou, J., Weerasekera, R., Zhao, B., Liu, X., Royannez, P., & Je, M. (2015). BIST methodology, architecture and circuits for pre-bond TSV testing in 3D stacking IC systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 62(1), 139-148. https://doi.org/10.1109/TCSI.2014.2354752

© 2004-2012 IEEE. This paper presents a built-in self test (BIST) methodology, architecture and circuits for testing Through Silicon Vias (TSVs) in 3D-IC systems prior to stacking in order to improve 3D-IC yield and reduce overall test cost. A scan s... Read More about BIST methodology, architecture and circuits for pre-bond TSV testing in 3D stacking IC systems.