BIST methodology, architecture and circuits for pre-bond TSV testing in 3D stacking IC systems

Wang, Chao; Zhou, Jun; Weerasekera, Roshan; Zhao, Bin; Liu, Xin; Royannez, Philippe; Je, Minkyu

Abstract

© 2004-2012 IEEE. This paper presents a built-in self test (BIST) methodology, architecture and circuits for testing Through Silicon Vias (TSVs) in 3D-IC systems prior to stacking in order to improve 3D-IC yield and reduce overall test cost. A scan switch network (SSN) architecture is proposed to perform pre-bond TSV scan testing in test mode, and operate as functional circuit in functional mode, respectively. In the SSN, novel test structures and circuits are proposed to address pre-bond TSV test accessibility issue and perform stuck-at-fault tests and TSV tests. By exploiting the inherent RC delay characteristics of TSV, a novel delay-based TSV test method is also proposed to map the variation of TSV-to-substrate resistance due to TSV defects to a test path delay change. Compared with state-of-art methods, the proposed BIST methodology addresses pre-bond TSV testing with a low-overhead integrated test solution which is compatible to existing 2D-IC testing method. The proposed BIST architecture and method can be implemented by standard DFT design flow and integrated into a unified pre-bond TSV test flow. Experiment results and robustness analysis are presented to verify the effectiveness of the proposed self-test methodology, architecture, and circuits.

Citation

Wang, C., Zhou, J., Weerasekera, R., Zhao, B., Liu, X., Royannez, P., & Je, M. (2015). BIST methodology, architecture and circuits for pre-bond TSV testing in 3D stacking IC systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 62(1), 139-148. https://doi.org/10.1109/TCSI.2014.2354752

• Journal Article Type: Article
• Acceptance Date: Aug 28, 2014
• Online Publication Date: Oct 8, 2014
• Publication Date: Jan 1, 2015
• Deposit Date: Feb 2, 2017
• Journal: IEEE Transactions on Circuits and Systems I: Regular Papers
• Print ISSN: 1549-8328
• Publisher: Institute of Electrical and Electronics Engineers
• Peer Reviewed: Peer Reviewed
• Volume: 62
• Issue: 1
• Pages: 139-148
• DOI: https://doi.org/10.1109/TCSI.2014.2354752
• Keywords: 3D IC, BIST, DFT, pre-bond TSV testing, TSV
• Public URL: https://uwe-repository.worktribe.com/output/839583
• Publisher URL: http://dx.doi.org/10.1109/TCSI.2014.2354752