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An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate

Weerasekera, Roshan; Katti, Guruprasad; Dutta, Rahul; Zhang, Songbai; Chang, Ka Fai; Zhou, Jun; Bhattacharya, Surya


Guruprasad Katti

Rahul Dutta

Songbai Zhang

Ka Fai Chang

Jun Zhou

Surya Bhattacharya


© 2016 IEEE. Through-silicon via (TSV) is an integral part of 2.5-D IC technology leveraged for multichip heterogeneous integration to achieve shorter interconnects, faster speed, and lower power consumption in the state-of-the-art circuit systems. These 2.5-D ICs use a silicon substrate, where there are no ground contacts unlike traditional 2-D ICs or 3-D ICs. TSVs in such electrically floating substrates call for new electrical models as well as improved parasitic extraction (PEX) methodology. Therefore, in this paper, an analytical capacitance model for TSVs in a 2.5-D IC is derived and validated. A TSV-to-TSV crosstalk expression is also validated and further extended to create an accurate 2.5-D IC PEX framework in addition to design robust grounding schemes, such that the TSV-to-TSV crosstalk coupling in an entire 2.5-D IC would be minimal even with floating silicon substrate. It is shown that a large number of regularly distributed power and ground TSVs provide an effective shield for the TSV-to-TSV crosstalk coupling and are highly recommended in the 2.5-D ICs.


Weerasekera, R., Katti, G., Dutta, R., Zhang, S., Chang, K. F., Zhou, J., & Bhattacharya, S. (2016). An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate. IEEE Transactions on Electron Devices, 63(3), 1182-1188.

Journal Article Type Article
Acceptance Date Jan 14, 2016
Publication Date Mar 1, 2016
Journal IEEE Transactions on Electron Devices
Print ISSN 0018-9383
Publisher Institute of Electrical and Electronics Engineers
Peer Reviewed Peer Reviewed
Volume 63
Issue 3
Pages 1182-1188
Keywords substrates, through-silicon vias, silicon, capacitance, crosstalk, integrated circuit modeling, analytical models
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