BIST methodology, architecture and circuits for pre-bond TSV testing in 3D stacking IC systems
(2014)
Journal Article
© 2004-2012 IEEE. This paper presents a built-in self test (BIST) methodology, architecture and circuits for testing Through Silicon Vias (TSVs) in 3D-IC systems prior to stacking in order to improve 3D-IC yield and reduce overall test cost. A scan s... Read More about BIST methodology, architecture and circuits for pre-bond TSV testing in 3D stacking IC systems.