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BIST methodology, architecture and circuits for pre-bond TSV testing in 3D stacking IC systems (2014)
Journal Article
Wang, C., Zhou, J., Weerasekera, R., Zhao, B., Liu, X., Royannez, P., & Je, M. (2015). BIST methodology, architecture and circuits for pre-bond TSV testing in 3D stacking IC systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 62(1), 139-148. https://doi.org/10.1109/TCSI.2014.2354752

© 2004-2012 IEEE. This paper presents a built-in self test (BIST) methodology, architecture and circuits for testing Through Silicon Vias (TSVs) in 3D-IC systems prior to stacking in order to improve 3D-IC yield and reduce overall test cost. A scan s... Read More about BIST methodology, architecture and circuits for pre-bond TSV testing in 3D stacking IC systems.